info.yaml

# Tiny Tapeout project information
project:
  title:        "Ternary 1.58-bit x 8-bit matrix multiplier"      # Project title
  author:       "ReJ aka Renaldas Zioma"
  discord:      "rzioma"
  description:  "Matrix multiplication block for 1.58 bit aka TERNARY weight LLMs"
  language:     "Verilog"
  clock_hz:     48000000       # Clock frequency in Hz (or 0 if not applicable)

  # How many tiles your design occupies? A single tile is about 167x108 uM.
  tiles: "3x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

  # Your top module name must start with "tt_um_". Make it unique by including your github username:
  top_module:  "tt_um_rejunity_1_58bit"
  
  # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
  source_files:
    - "config.v"
    - "1_58bit_mul.v"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
  # Inputs
  ui[0]: "packed weights LSB"
  ui[1]: "packed weights"
  ui[2]: "packed weights"
  ui[3]: "packed weights"
  ui[4]: "packed weights"
  ui[5]: "packed weights"
  ui[6]: "packed weights"
  ui[7]: "packed weights MSB"

  # Outputs
  uo[0]: "result LSB"
  uo[1]: "result "
  uo[2]: "result "
  uo[3]: "result "
  uo[4]: "result "
  uo[5]: "result "
  uo[6]: "result "
  uo[7]: "result MSB"

  # Bidirectional pins
  uio[0]: "(in) activations LSB"
  uio[1]: "(in) activations"
  uio[2]: "(in) activations"
  uio[3]: "(in) activations"
  uio[4]: "(in) activations"
  uio[5]: "(in) activations"
  uio[6]: "(in) activations"
  uio[7]: "(in) activations MSB"

# Do not change!
yaml_version: 6